Modern electronics systems have increased dramatically in density at virtually all levels. Integrated circuits have gone from densities of a few hundred transistors (or less) in the 1960's to densities of many millions of transistors in today's more complex microprocessors. Integrated circuit packaging density has gone from the relatively low density DIP packages (typically providing 8-40 pins on relatively large packages having a pin spacing of 0.1 inch) to today's fine-pitch technology (FPT), tape-automated bonding (TAB), and multi-chip modules (MCM's), providing hundreds of pins on relatively small packages. Conductive trace spacing and trace width on printed circuit boards (PCB's) has decreased dramatically, permitting large numbers of signals to be routed in a small space. Multi-layer PCB's and single and double-sided surface-mount techniques combine with high levels of integration and high-density integrated circuit packaging techniques to provide enormously dense electronic systems.
As electronics systems have "shrunk", they have become increasingly difficult to test. Traditional test methods include testing circuit board assemblies with so-called "bed-of-nails" testers which provide large numbers of spring-loaded contact pins which make contact with points on a printed circuit board (e.g., the pins of critical integrated circuits) to permit test access thereto. Modern fine-pitch packages, multi-layer PCB's, and double-sided surface mounting techniques frustrate attempts to test high-density electronic systems with bed-of-nails type testers.
Techniques which were once suitable for testing simpler integrated circuits with a few hundred gates are proving to be woefully inadequate with today's million-gate integrated circuits. Even user-defined semi-custom integrated circuits (ASIC's or Application Specific Integrated Circuits) routinely achieve densities of up to 100,000 gates, making them extremely difficult to test.
ASICs present a particularly difficult testing challenge. Such integrated circuits are often designed by combining pre-defined standard-cell functional blocks (often called "Core Cells") from a variety of sources with discrete logic to perform some desired function or group of functions. Even if standard test vectors or test strategies are provided with the individual standard cells (often standard cells come with no test data whatsoever) their internal connections to one another on the ASIC are often inaccessible at pins of the ASIC, dramatically complicating the test scenario.
One technique which is commonly used to gain access to standard cells on an ASIC is known as "MUX isolation" whereby a test mode or test signal is provided so that certain pins of the ASIC change function in the test mode. Multiplexers are used in the test mode to connect the ordinarily inaccessible signals of the standard cell(s) to pin of the ASIC. When the test signal (or mode) is removed, the pins revert to their normal functions. The MUX isolation technique is sometimes impractical or impossible, for example, when there are more signals at the periphery of a standard cell than there are pins on the ASIC containing it.
Another technique used for testing of ASICs is a "full-scan" design, whereby every flip-flop of a logic circuit has a multiplexer placed at its input so that in the presence of a test signal, all of the flip-flops are strung together into a shift register. This shift register is then used to clock in test patterns (stimuli) and to clock out test results (responses).
The full-scan test architecture assumes a fully-synchronous design, and is less beneficial for designs which include asynchronous logic, or which are not clocked by a common clock. Further, if a standard cell is not originally designed for full-scan testing, then modifying it to adapt it to full-scan testing can seriously alter its internal timing, possibly causing it to fail, or to slow unacceptably. Another problem with full-scan testing is that it only provides access to internal nodes and does not provide observability of the signals at the periphery of the standard cell, which may be several levels of logic removed from the flip-flops of the standard cell.
The "key" issues in testing a complex system (whether a circuit board, a standard integrated circuit, or an ASIC) are "controllability" and "observability" of critical elements in the system. "Controllability" is the ability to cause specific patterns of signals (stimulus) to be applied to the critical elements. "Observability" is the ability to determine that the critical elements have responded appropriately (response) to those patterns of signals.
Elaborate techniques such as reachability analysis have been developed to determine whether or not a particular element in the interior of a circuit design can be exercised ("reached") from the external interface to the circuit, and how (if possible) the operation of that particular element may be monitored. If a reachability analysis shows that a particular circuit element is not reachable (not controllable) or cannot be monitored (not observable) then the circuit design may be altered to provide test access to that element. This technique, however, is highly interactive (with the designer) and labor-intensive, and does not necessarily provide optimal or even near optimal test architectures.
An approach which addresses the access problem in testing complex printed circuit boards is known as "Boundary Scan" or JTAG type testing. The test architecture which defines one such boundary scan test technique is given in IEEE Standard No. 1149.1 Test Access Port (TAP) specification. Boundary-scan techniques, such as that described in the IEEE Standard, permit access to nodes (signals) of an electronic assembly by electrical rather than physical means. According to the IEEE TAP specification, four pins are added to each boundary-scan equipped integrated circuit (IC): a serial Test Data Input (TDI) signal, a serial Test Data Output (TDO) signal, a Test Mode Select (TMS) signal, and a Test Clock (TCK) signal. These pins control the operation of a Test Access Port (TAP) comprising a (relatively) small amount of on-chip circuitry added to the normal logic of each such integrated circuit. Portions of the TAP circuitry known as boundary-scan "cells" are interposed between the input/output signals of the logic of the integrated circuit and their respective input/output pins. The TAP includes one boundary-scan "cell" for each of the functional input/output pins of the integrated circuit and a TAP controller. The boundary-scan cells are arranged in a serially-connected shift-register chain by which test data may be shifted into and out of the integrated circuit. The TAP controller is essentially a finite-state machine which controls and configures all test operations performed via the boundary scan cells.
The four test pins, TDI, TDO, TMS, and TCK, connect to the on-chip TAP. The TMS and TCK operate together to clock chip-state data into the TAP controller, which in turn tells the TAP what mode of operation to assume. Depending upon the state (mode) of the TAP, data on the TDI line can go to pin-data registers in the boundary-scan cells, to bypass registers associated with the boundary scan cells or to any other registers accessible to the TAP. The bypass registers are provided to permit individual boundary scan cells to be bypassed and "removed" from the serially connected shift-register chain of boundary-scan cells (until reinstated by changing the contents of the bypass register). The data registers are used to "force" test data onto input signals of the functional logic of the integrated circuit. Among the modes assumable by the TAP is a test isolation mode whereby the input (and output) pins of the integrated circuit may be logically "disconnected" from the input (and output) signals of the logic of the integrated circuit, logically replacing the "broken" connections with connections to the data registers of the boundary scan cells. After operating the integrated circuit with the "forced" test data in the boundary-scan cells, output signals may then be sampled into their associated boundary-scan cells (using another mode of the TAP) and shifted out of the integrated circuit on the TDO pin for external analysis.
FIG. 1 is a block diagram of a prior-art integrated circuit 100 which employs a boundary-scan test architecture according to IEEE Standard 1149.1. An integrated circuit package 110 is shown having six input signal pins 120a, 120b, 120c, 120d, 120e, and 120f, six output signal pins 125a, 125b, 125c, 125d, 125e, and 125f, and four test interface pins 170 (TDI, or "Test Data In"), 175 (TDO, or "Test Data Out"), 180 (TMS, or "Test Mode Select"), and 185 (TCK, or "Test Clock"). Functional logic 150 on an integrated circuit die within the package 110 has six input signals 140a, 140b, 140c, 104d, 140e, and 140f, and six output signals 145a, 145b, 145c, 145d, 145e, and 145f. Each of the input and output signals is connected to a pin of the package 110 via a boundary scan cell. Input signal 140a is connected to input pin 120a via a boundary scan cell 130a. Input signal 140b is connected to input pin 120b via a boundary scan cell 130b. Input signal 140c is connected to input pin 120c via a boundary scan cell 130c. Input signal 140d is connected to input pin 120d via a boundary scan cell 130d. Input signal 140e is connected to input pin 120e via a boundary scan cell 130e. Input signal 140f is connected to input pin 120f via a boundary scan cell 130f. Output signal 145a is connected to output pin 125a via a boundary scan cell 135a. Output signal 145b is connected to output pin 125b via a boundary scan cell 135b. Output signal 145c is connected to output pin 125c via a boundary scan cell 135c. Output signal 145d is connected to output pin 125d via a boundary scan cell 135d. Output signal 145e is connected to output pin 125e via a boundary scan cell 135e. Output signal 145f is connected to output pin 125f via a boundary scan cell 135f.
A Test Access Port (TAP) 165 comprising the twelve boundary-scan cells 130a-130e, 135a-135e, and a Test Access Port controller 160 is connected to the four test pins TDI, TDO, TMS, and TCK, (170, 175, 180, and 185, respectively). The Test Access Port controller logic 160 controls the operational state (mode) of the TAP 165 according to logic signals received via the test pins. The TAP controller 160 is essentially a finite state machine integrated on the integrated circuit die with the functional logic 150 for the purpose of controlling test-related operation of the integrated circuit 100. The four test interface pins 170, 175, 180, and 185 are completely separate from the "normal" functional pins (i.e., 120a-120f and 125a-125f) of the integrated circuit 100 and provide a completely isolated test interface which does not interfere in any way with the normal operation of the integrated circuit.
The boundary scan cells 130a-130f and 135a-135f are arranged into a serially-connected shift-register chain beginning at the TDI (Test Data Input) pin 170, and ending at the TDO (Test Data Out) pin 175 in the following order: 130a, 130b, 130c, 103d, 130e, 130f, 135f, 135e, 135d, 135c, 135b, 135a. The boundary scan cells (130a-130f, 135a-135f) permit the input and output signals (140a-140f and 145a-145f, respectively) to be isolated from their respective input and output pins (120a-120f and 125a-125f, respectively), and provide for test data patterns to be shifted into the serially connected chain via the TDI and TCK test pins (170 and 185, respectively) and applied to the input signals (140a-140f) of the functional logic 150. After the test data is shifted in and applied to the input signals 140a-140f, the functional logic is exercised and resulting data patterns on output signals (145a-145f) are sampled into their respective boundary-scan cells (135a-135f) and shifted out of the chain via the TDO pin. Preferably, boundary-scan cells associated with output signals (e.g., cell 135a associated with output signal 145a) are located towards the end of the serially connected chain so that test result signals are closer to the TDO pin and are accessible with the smallest number of shift clocks possible.
FIG. 2 is a circuit diagram of a small electronic system 200 comprising two boundary-scan equipped integrated circuits 210a and 210b each comprising Functional Logic and a dozen boundary scan cells like circuit 110, and logic circuitry 220 comprising a D-type flip-flop 222 and two logic NAND gates 224 and 226. A boundary-scan test strategy is applied to the system 200. The data input (D) of flip-flop 222 is connected by a line 230 to an output signal of the integrated circuit 210a. The clock input (&gt;) of the flip-flop 222 is connected by a line 232 to another output of the integrated circuit 210a. The two NAND gates 224 and 226 are connected and configured as an R-S latch. One input of this R-S latch is connected via a line 234 to an output of the integrated circuit 210a. The other input of this R-S latch is connected via a line 244 to an output of the integrated circuit 210b. One output of the R-S latch is connected to a line 242 input terminal of the integrated circuit 210b, and the other output of the R-S latch is connected to a line 236 input terminal of the integrated circuit 210a.
Four test pins are provided on each of the two integrated circuits. The integrated circuit 210a has a TDI pin 270a, a TDO pin 275a, a TMS pin 280a, and a TCK pin 285a. The integrated circuit 210b has a TDI pin 270b, a TDO pin 275b, a TMS pin 280b, and a TCK pin 285b. The TDO pin 275a of the integrated circuit 210a is connected via a line 260 to the TDI pin 270b of the integrated circuit 210b, thus creating a long serial boundary-scan chain beginning at a serial data input line 294 connected to the TDI pin 270a of the integrated circuit 210a and ending at a serial data output line 296 connected to the TDO pin 275b of the integrated circuit 210b. The TMS pins 280a and 280b of the two integrated circuits 210a and 210b, respectively, are connected together in parallel via a line 290. The two TCK pins 285a and 285b of the two integrated circuits 210a and 210b are connected together in parallel via a line 292.
Testing of the system is accomplished by using the TMS and TCK signals to place the two integrated circuits 210a and 210b into a test mode, then clocking configuration and test data into the boundary-scan serial chain via the serial data input line 294. The integrated circuits 210a and 210b are then placed into an execution mode whereby they may be exercised with the test data. The integrated circuits are then placed into another mode whereby output signals of the integrated circuits 210a and 210b are sampled into the boundary-scan serial chain, and shifted out on the serial data output line 296. Both chips are tested in parallel.
Assuming that it is possible to use the boundary-scan chain to force output signals to the pins of the integrated circuits 210a and 210b (IEEE std. no 1149.1 provides a definition of a boundary-scan technique capable of this) the logic circuitry 220 located between the two chips may be similarly tested in a separate test operation.
Although the IEEE standard boundary-scan technique (or any boundary-scan technique, for that matter) may be applied to an ASIC, it does not solve the inherent problems in testing ASICs. Boundary-scan only provides access to the periphery of an integrated circuit, not to the internal nodes thereof, and is primarily intended to isolate the integrated circuit from other circuitry in a larger system. However the problem of testing the ASIC itself is not addressed by boundary-scan techniques.
Full-scan design may be applied to an ASIC, which does provide for good controllability and observability, but some standard cells are not initially designed with full-scan testing capability. Modification of the designs of the standard cells can be time consuming. Determining a suitable set of test vectors for such a modified design can be even more complicated and time consuming. There is no simple technique for translating a set of test vectors for a standard cell into test vectors for the standard cell after re-design for full-scan capability. In fact, the original test vectors may be completely useless for the purposes of full-scan testing.
Compounding the problem of testing ASICs is that different standard cells incorporated into a single ASIC may be equipped with incompatible test strategies. For example, a single ASIC may incorporate one standard cell design with full-scan test capability, another with CBIST (another test structure) test capability, and another with no particular test strategy at all. Test vectors might be provided by the supplier of the standard cell designs for each of the standard cells, but the application of these test vectors assumes that each and every one of the "pins" or external signals of the associated standard cell is independently accessible. Internal connections and "hidden" connections (connections between the standard cells and with other logic) within the ASIC prevent ready access to these signals. While MUX isolation may be used in some cases to provide test access to these signals, it may be impractical or impossible to provide access to all of the signals of all of the standard cells at once. Assuming, then, that the standard cells can be made accessible at the pins of the ASIC only one at a time, it is necessary to test the standard cells one at a time, rather than in a more desirable parallel fashion.
While these techniques, at best, provide for adequate testing of standard cells in an ASIC, they do nothing to test any discrete user logic between the standard cells. As a result, it may be necessary to design specialized test circuitry around the user logic to permit it to be tested.